1. Field of the Invention
This invention relates generally to the cell structure, device configuration and fabrication process of power semiconductor devices. More particularly, this invention relates to a novel and improved cell structure, device configuration and improved process for fabricating a trenched semiconductor power device with improved increased cell density by reducing a gate to source contact critical dimension (CD) requirement.
2. Description of the Related Art
As the cell density of the semiconductor power devices increases, several critical dimensions (CDs) such as the distance between the contact and the trench becomes a limiting factor. Specifically, the distance between the contact and the trench is to prevent an electrical short between the gate and the source. In a trenched MOSFET cell when a non-self aligned process is applied to manufacture the trench and the source contact, a misaligned tolerance must be provided to assure that there is no contact between the source contact and the trenched gate. However, the when a greater distance between the trenched gate and the source contact is applied to accommodate potential misalignment, the cell density of the semiconductor power device is limited to about 600M/in2 (six hundred million cells per square inch).
More specifically, the Applicant has filed another patent application Ser. No. 11/147,075 on Jun. 6, 2005 to improve the cell density by reducing the distance between the source contacts. An improved configuration of a MOSFET device is shown in FIGS. 1A and 1B wherein the distance between the source contacts are reduced by placing the source contact 45 in the source-body contact trenches opened in an oxide layer 35. As shown in FIG. 1B, the source-body contact trenches 45 extends into the body regions 25 thus contacting both the source regions 30 and the body regions 25 to provide improved and more reliable electric contacts. However, due to the concerns of misalignment, the source body contact trenches 45 must be opened with a minimum critical distance (CD) 40 away from the trenched gate 20 to prevent inadvertent electric contact between the source contact and the gate 20. The minimum CD requirement thus limits the further reducing of the cell dimensions. As that shown in FIGS. 1A and 1B, even with reduced distance between source contacts cell density of the MOSFET device the cell density is limited to approximately 600M/in2 (six hundred million cells per square inch). Further increase of cell density is very difficult due to this CD requirement to maintain a minimum distance between the source body contact trench 0 and the trenched gate 20.
Therefore, there is still a need in the art of the semiconductor device fabrication, particularly for trenched power MOSFET design and fabrication, to provide a novel cell structure, device configuration and fabrication process that would resolve these difficulties and design limitations. Specifically, it is desirable to maintain low gate resistance and in the meanwhile, it is further desirable to overcome the problems above discussed difficulties such that further increase of cell density of a trenched semiconductor power device can be achieved.